III-V materials are being actively studied for integration into both planar and three-dimensional, multi-gate metal-oxide-semiconductor field effect transistors (MOSFETs). Indium gallium arsenide (InGaAs), for example, is characterized by an extremely high electron mobility when compared to silicon, and is therefore attractive as a channel material. Nevertheless, despite the promise of increased device performance, manufacturable processing schemes capable of integrating III-V materials into MOSFET devices remains elusive because of several key technical challenges.
One such challenge occurs when trying to form self-aligned, low-resistance diffusion barriers that allow metallic contacts to be connected to source/drain features that are formed of III-V materials. While titanium and titanium nitride are used extensively as contact diffusion barriers for silicon-based technologies, titanium, when deposited on a feature comprising InGaAs, may alloy with elements of the InGaAs at temperatures as low as about 400° C. to form titanium arsenide compounds. These compounds are characterized by relatively high thin film resistivities. As a result, when depositing transition metals on InGaAs to form a diffusion barrier for metal contacts, the thermal budget of any subsequent processes associated with back-end-of-line (BEOL) processing may be severely restricted so as to avoid this unwanted alloying. Unfortunately, such a restriction does not lend itself to the manufacture of high-performance devices.